This invention relates generally to memories. More particularly, this invention relates to a new high speed memory circuit.
As microprocessors operate at faster speeds, demand for faster memories continues to increase. In one memory application, a microprocessor uses a memory as a look-up table that stores a normalized set of coefficients representing a mathematical expression such as a quadratic equation or square root. These types of memories are typically read only memories (ROMs) and are referred to as coefficient ROMs.
Other memory applications use random access memories (RAMs) to temporarily store instructions and data. For example, the data can include a status array. Since RAMs perform reads and writes in the same cycle the timing and design constraints are greater.
In FIG. 1, a typical memory 20 has an array of memory cells 22 that store information, such as instructions and data, as digital information having a logical one or a logical zero value. A logical one corresponds to a high voltage level, while a logical zero corresponds to a low voltage level. To access information stored in the array of memory cells 22, address signals, such as word line signals, are applied to the word lines 30.
In response to the address signals on the word lines, the array of memory cells 22 outputs the stored information for a row of cells on a bus 36 to a column multiplexor 38. In response to column select signals on a set 40 of column select lines 42-44, the column multiplexor 38 outputs a voltage corresponding to a selected column on bus 46. Typically, the voltage output by the column multiplexor 38 is very low and needs to be amplified for further processing. A sense amplifier 48 receives the signal on bus 46 and amplifies the signal to a predetermined level. In response to a sense amplifier enable signal, the sense amplifier outputs the amplified signals on yet another bus 50.
FIG. 1 was described with respect to a single selected bit. To output a set of bits, such as a byte or a word, memories typically have a large memory array coupled to multiple column multiplexors. Each column multiplexor responds to the same set of column select lines and is associated with a separate sense amplifier.
FIG. 2 illustrates the memory of FIG. 1 in more detail. The array 22 of memory cells (cell) has m rows 52, 54, 56, and n columns, 62, 64, 66. Each cell is connected to a bit line and a word line. Word line 0 (WL0) 32, word line 1 (WL1) 33 and word line mxe2x88x921 (WLmxe2x88x921) 34 connect to the memory cells of rows 52, 54 and 56, respectively.
The memory cells in the array 22 output a differential signal. Therefore each bit line is associated with two traces or linesxe2x80x94a primary line 72, 74, 76 which carries one side of the differential signal and a complementary line 82, 84, 86 which carries the complement or other side of the differential signal. For example, Bit line 0 (BL0) 72, Bit line 1 (BL1) 74 and Bit line nxe2x88x921 (BLnxe2x88x921) 76 and their complements {overscore (BL0)} 82, {overscore (BL1)} 84 and {overscore (BLnxe2x88x921+L )} 86, connect to the memory cells of columns 62, 64, and 66, respectively.
All cells in a column connect to the same bit line, and all cells in a row connect to the same word line. For example, all cells in column 62 connect to lines 72 and 82; and, all cells in row 52 connect to word line 32. When the word line is enabled, the voltage stored in that cell is output on the respective bit line to the column multiplexor 38.
In the column multiplexor 38, passgate blocks 92, 94 and 96 connect to columns 62, 64 and 66, respectively. In each passgate block 92, 94 and 96, PMOS transistors 102, 103, 104, 105, 106 and 107, are connected in series with each bit line, BL072, {overscore (BL0)} 82, BL174, {overscore (BL1)} 84, BLnxe2x88x921 76 and {overscore (BLnxe2x88x921+L )} 86, respectively. A column select signal, col 0, col 1 and col n, is applied to the gates of the PMOS transistors of each passgate block 92, 94 and 96, respectively, which causes each passgate block 92, 94 and 96 to output a differential signal. The differential outputs of the passgate blocks 92, 94 and 96, are connected and supplied to the sense amplifier 48. Since only one column select signal, col 0, col 1 and col nxe2x88x921, is active at a time to select a column 62, 64, 66, respectively, only one differential signal is applied to the sense amplifier 48.
As shown in FIG. 3, one commonly used memory cell 110 has a pair of cross-coupled inverters, 112, 114, that act as a latch 116 to store a voltage representing a logical one or a logical zero. One end 118, 120 of the latch 116 outputs a logical one while the other end, 120, 118, respectively, outputs the complement, a logical zero. In the memory cell 110, the complementary signals output by the latch 116 are used as a differential signal on lines 118 and 120 to represent a logical one value or a logical zero.
A write port 121 is used to store data in the latch 116. First and second access transistors, NMOS transistors 122 and 124, respectively, connect to the latch 116. The write word line 126 connects to the gate of each access transistor 122, 124. To store data in the memory cell, a write word line signal is asserted on the write word line 126 and a differential data signal is input via the NMOS access transistors, 122 and 124, on the write bit lines 128 and 130, respectively.
To sense the data, a read word line signal is asserted on the read word line 132 which is connected to the gates of a pair of NMOS passgate transistors 134, 135. The NMOS passgate transistors 134, 135 form a read port 136. The read word line signal is asserted by applying a predetermined voltage, such as a logical one, to the read word line 132. In response to the assertion of the read word line signal, the end of the latch 116 storing a logical one (a high voltage level) will pull up the voltage of the associated line through one of the passgate transistors to the high voltage level (a logical one level). The end of the latch 116 storing a logical zero value (low voltage level) will pull down the voltage of the associated line through the other passgate transistor to the logical zero.
For example, if the latch 116 stores a logical one, when the read word line signal is asserted, read bit line 138 will be pulled up to a logical one, while read bit line 139 will be pulled down to a logical zero value. In contrast, if the latch 116 stores a logical zero value, when the read word line is asserted, read bit line 138 will be pulled down to a logical zero, while read bit line 139 will be pulled up to a logical one.
In memory circuits, capacitive effects reduce speed. One major capacitive effect is diffusion loading. NMOS and PMOS transistors have some amount of diffusion capacitance or diffusion loading. To form the source and drain of the transistors, the source and drain regions are doped with n+ and p+ ions, and these regions are referred to as diffusion regions. Diffusion regions have a diffusion capacitance between the diffusion region and the substrate. The amount of diffusion capacitance is related to the voltage between the diffusion regions and the substrate, as well as the effective area of the diffusion region and the depth of the diffusion region.
Referring back to FIG. 2, the diffusion loading of a particular bit line is related to the number of cells connected to that bit line. For example, bit line 0 (BL0) 72 connects to m cells. Therefore, if each cell has a diffusion capacitance of Cd, the total diffusion loading on the bit line 0 (BL0) 72 is Cd multiplied by m (mxc2x7Cd). The diffusion loading limits the speed at which the memory operates.
In the memory 20 of FIG. 2, a sense amplifier enable signal is used to control the sense amplifier 48. In this architecture, the sense amplifier 48 is turned on at a predetermined time to ensure that the sense amplifier 48 is not sensing too early. Thus the differential design needs a predetermined amount of overhead time to ensure that the bit line signals are not sensed too early. This also increases the complexity of the circuitry. This design complexity is typically accompanied by circuit fabrication complexity.
In view of the foregoing, it would be highly desirable to provide a memory circuit that operates at a faster speed with reduced diffusion loading of the bit lines. It would also be desirable to provide a memory circuit that does not use a sense amplifier enable signal. Such a circuit would operate at an increased speed, reduce timing problems and have a simpler design.
A memory has an array of memory cells arranged in rows and columns. In the columns, bit lines are connected to the memory cells in an alternating manner in which the memory cells in a column connect to different bit lines. Output circuitry that connects to the array of memory cells eliminates the need for a sense amplifier enable signal. In this way, by eliminating the need for the sense amplifier enable signal, the memory operates at an increased speed with fewer timing problems and has a simpler design. In addition, since the number of memory cells connected to each bit line is reduced, diffusion loading on the bit lines is reduced, thereby increasing memory speed.
In particular, in the array, the memory cells are arranged in rows and columns. A word line is coupled to each memory cell in each row. Bit lines are coupled to the memory cells in each column. Each bit line is coupled to a mutually exclusive subset of memory cells in the column, wherein the memory cells of a row, as selected memory cells, output a cell voltage on their coupled bit line when the word line is asserted. A multiplexor receives the cell voltage from the selected memory cells on the bit lines. The multiplexor is responsive to column select signals to select one column as a selected column, and output a multiplexor voltage corresponding to the cell voltage of the memory cell of the selected column.
In yet another embodiment, sense amplifiers are placed between the array of memory cells and the multiplexor. The sense amplifiers are coupled to the memory cells of the columns. Each mutually exclusive subset of memory cells is coupled to one of the sense amplifiers to receive the cell voltage output by the selected memory cells and to generate an amplified voltage. The multiplexor receives the amplified voltage instead of the cell voltage.
In this way, by placing a sense amplifier at the end of each bit line, the sense amplifier enable signal is eliminated and the complexity of the circuitry is reduced. In this approach the multiplexor selection is inherent to the design because only one bit line of multiple bit lines in a column is selected at a time.
In another alternate embodiment, single-ended memory cells are used. In this way, differential output from the memory cells is not required and the number of lines, and therefore circuit complexity, is reduced.
The alternating array of memory cells improves the speed of operation of the memory by reducing the diffusion loading on the bit lines by about at least one-half. In the multiplexor, each column select block receives one of the column select signals. Therefore, even though the columns have multiple bit lines, one column select signal still controls the output from a column.